B&B Electronics 4 Channel Input Buffer Board SDAIBB Manuel d'utilisateur télécharger pdf (Page 21)

SIS8300 Firmware Aspects

The SIS8300 MTCA.4 digitizer family was de-

veloped in co-operation with DESY for a variety

of different applications at the European XFEL

and demonstrator setups. A modular ﬁ rmware

approach allows for customization targeting the

requirements of the speciﬁ c application. An over-

view of the ﬁ rmware building blocks is given in

the diagram below.

SIS8300 Firmware Building Blocks

DDR2 Memory Controller

The memory controller block supports the 512 Mbyte and

the 1 GByte memory options of the SIS8300. It interfaces

to the 4-lane PCI Express with a read/write DMA inter-

face. The histogramming memory controller supports an

update rate of 5 MHz (20 MHz within one memory page

amid differing three lowest order bits).

Full Custom Firmware

Feel free to inquire about a full custom ﬁ rmware design

development or customized application ﬁ rmware for the

SIS8300 digitizer to meet the requirements for your appli-

cation.

The UCF ﬁ le and required information about on board

peripherals is provided to those who would like to deve-

lop their own full custom ﬁ rmware design for the card in

house.

SIS8300 Memory Controller Block

Screen Shot of Generic Firmware SIS8300

ROOT GUI (under LINUX)

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B&B Electronics 4 Channel Input Buffer Board SDAIBB Manuel d'utilisateur Page 21